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Simulating Tomorrow’s Chips

MIT News (04/13/12) Larry Hardesty

Researchers at the Massachusetts Institute of Technology’s (MIT’s) Computer Science and Artificial Intelligence Laboratory have developed Arete, a method for improving the efficiency of hardware simulations of multicore chips.  The researchers say Arete guarantees the simulator will not fall into a deadlock state in which cores get stuck waiting for each other to give up system resources.  Arete also could make it easier for designers to develop simulations and for outside observers to understand what those simulations are meant to accomplish.  The method involves a circuit design that enables the ratio between real clock cycles and simulated cycles to fluctuate as needed, which allows for faster simulations and more economical use of the field-programmable gate array’s (FPGA’s) circuitry.  “What we’re proposing is, instead of having this in your head, let’s start with a specification,” says MIT graduate student Asif Khan.  The researchers’ high-level language, known as StructuralSpec, builds on the BlueSpec hardware design language developed at MIT in the late 1990s.  StructuralSpec users provide a high-level specification of a multicore model, and the program produces the code that implements that model on an FPGA.



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