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Intel Charts Its Multicore and Manycore Future for HPC.

HPC Wire (12/01/10) Michael Feldman

Intel recently mapped out its strategy for multicore and manycore architectures. Intel’s Rajeeb Hazra says the company’s objective “is to bring to the high-performance computing (HPC) marketplace innovations that drive essentially all of HPC, from the very high end of supercomputing to volume workstations.” Intel’s new Many Integrated Core (MIC) architecture is positioned to be a primary tool in that effort, with Hazra noting that it will form the foundation for its manycore processor design for the next 10 years and beyond. MIC is designed to pack many floating point operations into an extremely energy-efficient bundle. Hazra points out that performance upgrades in the top 100 supercomputers over the last decade were chiefly facilitated through the scale-out model, but this solution will be practical for only a few more years. He says Intel plans to provide the performance per watt similar to that of general-purpose computing on graphics processing units, but in an x86 architecture that enables applications to migrate from single-threaded codes to highly-parallel codes without revising the underlying model. Intel will provide compiler and runtime software support for MIC, as well as a common set of development tools to be employed across the Xeon and MIC products, with a goal of maximizing the productivity of programmers.



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